Ascenium Inc
General-Purpose Accelerator (GPA) — a hardware accelerator chip that replaces CPUs and accelerates generic software workloads beyond AI
New patent ·
- Sector
- Semiconductors
- Headquarters
- CAMPBELL, CA
- Founded
- 2019
- Latest Form D
- $3M, Nov 2021
- Total capital
- $23M
- Federal grants
- None on recordNo awards found in SBIR/STTR, NIH, NSF or DoD records.
- Private capital raised
- $23M
- 2 Form D · last Nov 2021
- 60 months since last filing
- Federal contracts
- None on recordNo federal contract awards found.
- Granted patents
- 8
- 32 pending · first 2022
- Rank in peer group#55 of 224
Capital timeline
Latest events
- Private capital raisedForm D · SEC · 2nd filing$3M
- Private capital raisedForm D · SEC · 1st filing$20M
Node area is scaled to amount. Form D reports securities sold, which can differ from an announced round; filings are numbered in the order they were made.
Standing among 224 peers
Line = medianSemiconductors · Device
- Granted patents#55 · top 25%
Cumulative measures favor older companies. Rankings describe position today, not outcome. Below the median, ranks show as a band rather than a number.
Founders and team
Researcher links verified by same-company patents and grants- Peter FoleyResearcherExecutive Officer, DirectorLinked by 1 patent
- Andrew RobinDirectorNamed in SEC Form D filings
- Espen FjogstadDirectorNamed in SEC Form D filings
- Robert W. LishmanExecutive Officer, DirectorNamed in SEC Form D filings
- Robert W. MyklandExecutive Officer, DirectorNamed in SEC Form D filings
What it has protected
USPTO · 8 granted of 40- New patentParallel Processing Architecture For Branch Path SuppressionUSPTOUS 12,748,638
- GrantedParallel Processing Architecture With Block Move SupportUSPTOUS 12,743,377
- GrantedLoad Latency Amelioration Using Bunch BuffersUSPTOUS 12,730,668
Show all 40 patent records
- Parallel Processing Architecture For Branch Path SuppressionSep 29, 2026 · US 12,748,638Granted
- Parallel Processing Architecture With Block Move SupportSep 22, 2026 · US 12,743,377Granted
- Load Latency Amelioration Using Bunch BuffersSep 8, 2026 · US 12,730,668Granted
- Highly Parallel Processing Architecture With Out-of-order ResolutionAug 11, 2026 · US 12,705,092Granted
- Generating Iteration Transfer Information For Code Execution With A Compute Slice MicroarchitectureMay 21, 2026 · Application 19446865Pending
- Parallel Processing Architecture With Distributed Register FilesMar 17, 2026 · US 12,578,991Granted
- Compute Element Processing Using Control Word TemplatesDec 23, 2025 · US 12,504,958Granted
- Memory Dependence Prediction In A Parallel Architecture With Compute SlicesDec 18, 2025 · Application 19235822Pending
- Parallel Processing Using Hazard Detection And MitigationDec 9, 2025 · US 12,493,554Granted
- Global Memory Disambiguation For A Parallel Architecture With Compute SlicesNov 6, 2025 · Application 19197924Pending
- Local Memory Disambiguation For A Parallel Architecture With Compute SlicesOct 2, 2025 · Application 19093385Pending
- Compiler Generated Hyperblocks In A Parallel Architecture With Compute SlicesAug 21, 2025 · Application 19053495Pending
- Semantic Ordering For Parallel Architecture With Compute SlicesMar 13, 2025 · Application 18826260Pending
- Parallel Architecture With Compiler-scheduled Compute SlicesJan 16, 2025 · Application 18769478Pending
- Parallel Processing Architecture With Block Move BackpressureDec 19, 2024 · Application 18820425Pending
- Parallel Processing Architecture With Block Move SupportNov 21, 2024 · Application 18785026Pending
- Parallel Processing Hazard Mitigation AvoidanceAug 8, 2024 · Application 18640044Pending
- Parallel Processing Architecture For Branch Path SuppressionJun 13, 2024 · Application 18585156Pending
- Parallel Processing With Hazard Detection And Store ProbesMay 23, 2024 · Application 18426438Pending
- Parallel Processing With Switch Block ExecutionMar 7, 2024 · Application 18388875Pending
- Parallel Processing Architecture With Bin Packing Of Variable-length Compressed Control WordsJan 25, 2024 · Application 18236442Pending
- Parallel Processing Architecture With Memory Block TransfersDec 21, 2023 · Application 18239770Pending
- Parallel Processing Architecture With Dual Load Buffers And A Second Data CacheNov 23, 2023 · Application 18228001Pending
- Parallel Processing Architecture With Countdown TaggingNov 2, 2023 · Application 18220331Pending
- Parallel Processing Architecture With Split Control Word CachesOct 26, 2023 · Application 18215866Pending
- Parallel Execution Of Multiple Loops Using Precedence-tagged Control WordsSep 7, 2023 · Application 18195407Pending
- Autonomous Compute Element Operation Using BuffersJul 13, 2023 · Application 18124115Pending
- Reconfigurable Circuit Array Using Instructions Including A Fetch Configuration Data Portion And A Transfer Configuration Data PortiDec 20, 2022 · US 11,531,638Granted
- Parallel Processing Architecture Supporting With Compiler-set Control Word Bit Multicycle Atomic OperationsNov 24, 2022 · Application 17879827Pending
- Parallel Processing Architecture Using Distributed Register FilesSep 29, 2022 · Application 17840689Pending
- Program Execution With Coalesced Control Words For Parallel Branch Path ExecutionJul 7, 2022 · Application 17704056Pending
- Highly Parallel Processing Architecture Using Dual Branch ExecutionApr 7, 2022 · Application 17551276Pending
- Highly Parallel Processing Architecture With CompilerMar 10, 2022 · Application 17526003Pending
- Parallel Processing Architecture With Background LoadsMar 10, 2022 · Application 17500990Pending
- Highly Parallel Processing Architecture With Shallow PipelineMar 10, 2022 · Application 17465949Pending
- Parallel Processing Architecture With Memory Block TransfersApplication PCTUS2023031460Pending
- Parallel Processing Architecture With Block Move BackpressureApplication 63536144Pending
- Parallel Processing Hazard Mitigation AvoidanceApplication PCTUS2024025310Pending
- Semantic Ordering For Parallel Architecture With Compute SlicesApplication 63537024Pending
- Parallel Processing Using Hazard Detection And MitigationApplication PCTUS2023036949Pending
Related companies, and why
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- Magwerks Vision Inc.Similar federal contract value in Semiconductors · null in contracts
Sources
Federal grants from SBIR/STTR, NIH, NSF and DoD records. Federal contracts from USAspending.gov. Private capital from SEC Form D. Patents from USPTO. Publications from OpenAlex. Regulatory activity from the Federal Register. Press matched on company name.
How to read this page
Figures show associations in public records, not causes or predictions. Nothing here is investment advice. An em-dash means no record was found under this company's name, not that none exists.
Data freshness
SEC Form D filings through . SBIR and STTR awards through .