Ventana Micro Systems Inc.
Automated immunohistochemistry and in situ hybridization systems for digital pathology
New patent ·
- Sector
- Medtech
- Headquarters
- SAN JOSE, CA
- Founded
- 2018
- Latest Form D
- $35M, Jun 2021
- Total capital
- $40.3M
- Federal grants
- None on recordNo awards found in SBIR/STTR, NIH, NSF or DoD records.
- Private capital raised
- $40.3M
- 2 Form D · last Jun 2021
- 64 months since last filing
- Federal contracts
- None on recordNo federal contract awards found.
- Granted patents
- 40
- first 2024
- Rank in peer group#22 of 1112
Capital timeline
Latest events
- Private capital raisedForm D · SEC · 2nd filing$35M
- Private capital raisedForm D · SEC · 1st filing$5.2M
Node area is scaled to amount. Form D reports securities sold, which can differ from an announced round; filings are numbered in the order they were made.
Standing among 1112 peers
Line = medianMedtech · Device
- Granted patents#22 · top 2%
Cumulative measures favor older companies. Rankings describe position today, not outcome. Below the median, ranks show as a band rather than a number.
Founders and team
From SEC Form D filings- Balaji BakthavatchalamExecutive Officer, DirectorNamed in SEC Form D filings
- Jeffrey HarrellExecutive Officer, DirectorNamed in SEC Form D filings
- Ranganathan SudhakarDirectorNamed in SEC Form D filings
- Ravikrishna CherukuriDirectorNamed in SEC Form D filings
- Sehat SutardjaDirectorNamed in SEC Form D filings
What it has protected
USPTO · 40 granted of 40- New patentProcessor That Mitigates Side Channel Attacks By Refraining From Allocating An Entry In A Data Tlb For A Missing Load Address When The Load Address Misses Both In A Data Cache Memory And In The Data Tlb And The Load Address Specifies A Location Without A Valid Address Translation Or Without Permission To Read From The LocationUSPTOUS 12,769,550
- New patentNon-cacheable Access Handling In Processor With Virtually-tagged Virtually-indexed Data CacheUSPTOUS 12,762,064
- GrantedMicroprocessor That Performs Mid-fetch Block Restart Abort ProcessingUSPTOUS 12,693,864
Show all 40 patent records
- Processor That Mitigates Side Channel Attacks By Refraining From Allocating An Entry In A Data Tlb For A Missing Load Address When The Load Address Misses Both In A Data Cache Memory And In The Data Tlb And The Load Address Specifies A Location Without A Valid Address Translation Or Without Permission To Read From The LocationOct 20, 2026 · US 12,769,550Granted
- Non-cacheable Access Handling In Processor With Virtually-tagged Virtually-indexed Data CacheOct 13, 2026 · US 12,762,064Granted
- Microprocessor That Performs Mid-fetch Block Restart Abort ProcessingJul 28, 2026 · US 12,693,864Granted
- Physical Address Proxy Reuse ManagementMar 3, 2026 · US 12,566,702Granted
- Power Management Of Devices With Differentiated Power Scaling Based On Relative Power Benefit EstimationFeb 24, 2026 · US 12,560,993Granted
- Processor That Mitigates Side Channel Attacks By Preventing Cache Memory State From Being Affected By A Missing Load Operation By Inhibiting Or Canceling A Fill Request Of The Load Operation If An Older Load Generates A Need For An Architectural ExceptionJan 13, 2026 · US 12,524,538Granted
- Microprocessor That Builds Multi-fetch Block Macro-op Cache Entries In Two-stage ProcessDec 16, 2025 · US 12,498,928Granted
- Microprocessor That Performs Partial Fallback Abort Processing Of Multi-fetch Block Macro-op Cache EntriesDec 16, 2025 · US 12,498,929Granted
- Prediction Unit That Predicts Successor Fetch Block Start Address Of Multi-fetch Block Macro-op Cache EntryDec 16, 2025 · US 12,498,933Granted
- Microprocessor That Builds Consistent Loop Iteration Count Unrolled Loop Multi-fetch Block Macro-op Cache EntriesDec 16, 2025 · US 12,498,926Granted
- Microprocessor That Allows Same-fetch Block Start Address Co-residence Of Unrolled Loop Multi-fetch Block Macro-op Cache Entry And Loop Body Macro-op Cache Entry Used To Build SameDec 16, 2025 · US 12,498,927Granted
- Physical Address Proxy (pap) Residency Determination For Reduction Of Pap ReuseDec 16, 2025 · US 12,499,050Granted
- Microprocessor That Builds Inconsistent Loop Iteration Count Unrolled Loop Multi-fetch Block Macro-op Cache EntriesDec 9, 2025 · US 12,493,466Granted
- Using Physical Address Proxies To Accomplish Penalty-less Processing Of Load/store Instructions Whose Data Straddles Cache Line Address BoundariesDec 9, 2025 · US 12,493,558Granted
- Microprocessor That Extends Sequential Multi-fetch Block Macro-op Cache EntriesDec 9, 2025 · US 12,493,469Granted
- Microprocessor That Performs Mid-macro-op Cache Entry Restart Abort ProcessingDec 9, 2025 · US 12,493,468Granted
- Prediction Unit That Predicts Branch History Update Information Produced By Multi-fetch Block Macro-op Cache EntryDec 2, 2025 · US 12,487,926Granted
- Store-to-load Forwarding Correctness Checks Using Physical Address Proxies Stored In Load Queue EntriesDec 2, 2025 · US 12,487,936Granted
- Virtually-indexed Cache Coherency Using Physical Address ProxiesDec 2, 2025 · US 12,487,939Granted
- Prediction Unit With First Predictor That Provides A Hashed Fetch Address Of A Current Fetch Block To Its Own Input And To A Second Predictor That Uses It To Predict The Fetch Address Of A Next Fetch BlockDec 2, 2025 · US 12,487,830Granted
- Method And Apparatus For Deskewing Die To Die Communication Between System On Chip DevicesNov 25, 2025 · US 12,481,310Granted
- Microprocessor That Performs Selective Multi-fetch Block Macro-op Cache Entry InvalidationOct 21, 2025 · US 12,450,067Granted
- Microprocessor That Builds Sequential Multi-fetch Block Macro-op Cache EntriesOct 21, 2025 · US 12,450,066Granted
- Store-to-load Forwarding Correctness Checks At Store Instruction CommitAug 19, 2025 · US 12,393,426Granted
- Unforwardable Load Instruction Re-execution Eligibility Based On Cache Update By Identified Store InstructionJun 17, 2025 · US 12,332,793Granted
- Performance And Power Efficient Processor When Switching Between Fetching From Decoded And Non-decoded Instruction SourcesMay 13, 2025 · US 12,299,449Granted
- Macro-op Cache Data Entry Pointers Distributed As Initial Pointers Held In Tag Array And Next Pointers Held In Data Array For Efficient And Performant Variable Length Macro-op Cache EntriesApr 22, 2025 · US 12,282,430Granted
- Microprocessor With Branch Target Buffer Whose Entries Include Fetch Block Hotness Counters Used For Selective Filtering Of Macro-op Cache AllocationsMar 18, 2025 · US 12,253,951Granted
- Microprocessor That Prevents Store-to-load Forwarding Between Different Translation ContextsFeb 18, 2025 · US 12,229,252Granted
- Microprocessor That Prevents Same Address Load-load Ordering Violations Using Physical Address ProxiesDec 31, 2024 · US 12,182,019Granted
- Branch Target Buffer Miss HandlingOct 15, 2024 · US 12,118,360Granted
- Physically-tagged Data Cache Memory That Uses Translation Context To Reduce Likelihood That Entries Allocated During Execution Under One Translation Context Are Accessible During Execution Under Another Translation ContextOct 15, 2024 · US 12,118,076Granted
- Using Physical Address Proxies To Handle Synonyms When Writing Store Data To A Virtually-indexed CacheOct 15, 2024 · US 12,117,937Granted
- Prediction Unit With First Predictor That Provides A Hashed Fetch Address Of A Current Fetch Block To Its Own Input And To A Second Predictor That Uses It To Predict The Fetch Address Of A Next Fetch BlockOct 1, 2024 · US 12,106,111Granted
- Virtually-indexed Cache Coherency Using Physical Address ProxiesSep 24, 2024 · US 12,099,448Granted
- Store-to-load Forwarding Correctness Checks Using Physical Address Proxies Stored In Load Queue EntriesSep 17, 2024 · US 12,093,179Granted
- Processor That Prevents Speculative Execution Across Translation Context Change Boundaries To Mitigate Side Channel AttacksSep 10, 2024 · US 12,086,245Granted
- Physical Address Proxy Reuse ManagementSep 10, 2024 · US 12,086,063Granted
- Unforwardable Load Instruction Re-execution Eligibility Based On Cache Update By Identified Store InstructionSep 3, 2024 · US 12,079,126Granted
- Using Physical Address Proxies To Accomplish Penalty-less Processing Of Load/store Instructions Whose Data Straddles Cache Line Address BoundariesSep 3, 2024 · US 12,079,129Granted
Related companies, and why
- Evofem Holdings, Inc.Similar federal contract value in Medtech · null in contracts
- Freespira, Inc.Similar federal contract value in Medtech · null in contracts
- Stroma Medical CorpSimilar federal contract value in Medtech · null in contracts
- Urotronic, Inc.Similar federal contract value in Medtech · null in contracts
- LUMINOPIA, INC.Similar federal contract value in Medtech · null in contracts
- Rivermark Medical, Inc.Similar federal contract value in Medtech · null in contracts
Regulatory activity · Medtech
- New Animal Drugs; Approval of New Animal Drug Applications; Withdrawal of Approval of New Animal Drug Application; Change of SponsorFood and Drug Administration
- Medical Devices; General and Plastic Surgery Devices; Classification of the Skin Patch for Treatment of HyperhidrosisFood and Drug Administration
- Medical Devices; Anesthesiology Devices; Classification of the Monitor for Opioid Induced Impairment of OxygenationFood and Drug Administration
- Medical Devices; Orthopedic Devices; Classification of the Medial Knee Implanted Shock AbsorberFood and Drug Administration
- Medical Devices; Neurological Devices; Classification of the External Lower Extremity Nerve Stimulator for Restless Legs SyndromeFood and Drug Administration
- Medical Devices; General Hospital and Personal Use Devices; Classification of the Infant Supine Sleep SystemFood and Drug Administration
Rules are matched to sector, not to company. Recent activity in a sector is context rather than a signal about this business — until rules are matched to what a company actually builds, the section is shown as context and nothing more.
Sources
Federal grants from SBIR/STTR, NIH, NSF and DoD records. Federal contracts from USAspending.gov. Private capital from SEC Form D. Patents from USPTO. Publications from OpenAlex. Regulatory activity from the Federal Register. Press matched on company name.
How to read this page
Figures show associations in public records, not causes or predictions. Nothing here is investment advice. An em-dash means no record was found under this company's name, not that none exists.
Data freshness
SEC Form D filings through . SBIR and STTR awards through .