SYNOPSYS INC
Electronic design automation (EDA) software for semiconductor design and verification
- Sector
- Semiconductors
- Headquarters
- Sunnyvale, CA
- Latest Form D
- $2.0B, Dec 2025
- Total capital
- $2.0B
- Federal grants
- None on recordNo awards found in SBIR/STTR, NIH, NSF or DoD records.
- Private capital raised
- $2.0B
- 1 Form D · last Dec 2025
- 11 months since last filing
- Federal contracts
- $126K
- 1 award · NASA
- Rank in Semiconductors#155 of 707
- Granted patents
- 39
- 1 pending · first 2026
- Rank in peer group#1 of 27
Capital timeline
Latest events
- Private capital raisedForm D · SEC · 1st filing$2.0B
- Federal contractNASA · Funds For The Following: Synplify And Hdl Actel Only - Perpetual Ne Maintenance Synplify And Hdl Xilinix Only - Perpetual Ne Maintenance Synplify Pro Xilinix Only - Perpetual Ne Maintenance Synphony Mod. Compiler Fpga - Perpetual Nodelodk Maintenance Synplify Xilinix Only - Perpetual Ne Maintenance Synplify Pro Av - Perpetual Nodelock Maintenance$126K
Node area is scaled to amount. Form D reports securities sold, which can differ from an announced round; filings are numbered in the order they were made.
Federal first
152months
from SYNOPSYS INC’s first federal award to its first private round.
- First federal award · Apr 2013
- NASA · $126K
- First Form D · Dec 2025
- $2.0B · 1st Form D
- Awards before first raise
- 1 award
An association in public records, not a cause or a prediction.
Standing among 27 peers
Line = medianSemiconductors · Software
- Granted patents#1 · top 4%
Cumulative measures favor older companies. Rankings describe position today, not outcome. Below the median, ranks show as a band rather than a number.
Founders and team
From SEC Form D filings- Aart J. de GeusExecutive Officer, DirectorNamed in SEC Form D filings
- Ajei J. GopalDirectorNamed in SEC Form D filings
- Bruce J. ChizenDirectorNamed in SEC Form D filings
- Janet G. LeeExecutive OfficerNamed in SEC Form D filings
- Janice J. ChaffinDirectorNamed in SEC Form D filings
- Jeannine P. SargentDirectorNamed in SEC Form D filings
Show all 14 people
- John G. SchwarzDirectorNamed in SEC Form D filings
- Luis J. BorgenDirectorNamed in SEC Form D filings
- Mercedes J. JohnsonDirectorNamed in SEC Form D filings
- Mike G. EllowExecutive OfficerNamed in SEC Form D filings
- Ravi G. VijayaraghavanDirectorNamed in SEC Form D filings
- Robert G. PainterDirectorNamed in SEC Form D filings
- Sassine GhaziExecutive Officer, DirectorNamed in SEC Form D filings
- Shelagh G. GlaserExecutive OfficerNamed in SEC Form D filings
What it has protected
USPTO · 39 granted of 40- New patentMemory Compaction To Reduce Emulation Model SizeUSPTOUS 12,769,446
- New patentEnhanced Cell Modeling for Waveform PropagationUSPTOUS 12,769,915
- New patentModeling Mandrel Tolerance In A Design Of A Semiconductor DeviceUSPTOUS 12,769,920
Show all 40 patent records
- Memory Compaction To Reduce Emulation Model SizeOct 20, 2026 · US 12,769,446Granted
- Enhanced Cell Modeling for Waveform PropagationOct 20, 2026 · US 12,769,915Granted
- Modeling Mandrel Tolerance In A Design Of A Semiconductor DeviceOct 20, 2026 · US 12,769,920Granted
- On-chip Supply Transient Drop And Supply Transient Bump DetectionOct 13, 2026 · US 12,761,252Granted
- Optimizing Machine Learning Classification Models For Resource Constraints In Electronic Design Automation (eda) Computer Aided Design (cad) FlowsOct 13, 2026 · US 12,762,321Granted
- Determining The Location Of Safety Mechanism Within A Circuit DesignOct 13, 2026 · US 12,762,319Granted
- Temporal Control Of Fault Functional VerificationOct 13, 2026 · US 12,762,322Granted
- Block Virtualization For Multi-threaded Electronic Design Automation Read/write Database AccessOct 13, 2026 · US 12,762,318Granted
- Identifying Potential Improvement Opportunities For Simulation Performance Of An Integrated Circuit DesignOct 13, 2026 · US 12,762,315Granted
- Analog References for High Voltage Input-Output with Improved Bias CurrentOct 13, 2026 · US 12,763,736Granted
- Block Virtualization For Multi-threaded Electronic Design Automation Read/write Database AccessOct 13, 2026 · US 12,762,054Granted
- Hardened Memory Device Noise ProtectionOct 13, 2026 · US 12,763,135Granted
- Error-correcting And Error-detecting Parity-check Matrix To Store A Known Bad Data Bit In A Memory SystemSep 29, 2026 · US 12,748,660Granted
- Statistical Graph Circuit Component Probability Model For An Integrated Circuit DesignSep 29, 2026 · US 12,748,908Granted
- Low Contention High Reference Offset Tolerant Level ShifterSep 22, 2026 · US 12,744,532Granted
- Methods And Systems For The Estimation Of The Computational Cost Of SimulationSep 17, 2026 · Application 19308726Pending
- Automated Multi-stage Design Flow Based On Final Quality Of ResultSep 15, 2026 · US 12,737,523Granted
- Memory Data InversionSep 15, 2026 · US 12,737,138Granted
- Input/output (io) Failsafe Protection Topology In Leaky Technology NodesSep 15, 2026 · US 12,738,940Granted
- High-speed Octal-rate Wireline TransmittersSep 8, 2026 · US 12,732,190Granted
- Statistical Timing Characterization Of Superconducting Electronic Circuit DesignsSep 8, 2026 · US 12,730,954Granted
- Adding Scalar Blinding In Elliptic Curve CryptographySep 8, 2026 · US 12,732,365Granted
- Analog Amplitude Control Circuit To Optimize Drive Level Of Crystal OscillatorSep 8, 2026 · US 12,732,146Granted
- Asynchronous Sar Adc With Detection And Correction Circuit For Large Amplitude Output Code ErrorsSep 8, 2026 · US 12,732,206Granted
- Josephson Junction StructuresSep 1, 2026 · US 12,727,393Granted
- Automatic Waiver Generation For Filtering Violations Reported By Static AnalysisSep 1, 2026 · US 12,724,950Granted
- License Server Caching For Checkout Of Floating LicensesSep 1, 2026 · US 12,724,853Granted
- Real Time View Swapping (rtvs) In A Mixed Signal SimulationSep 1, 2026 · US 12,724,951Granted
- Manufacturing Automatic Test Equipment And Field Ambient Comparison With Silicon Lifecycle Management SupportSep 1, 2026 · US 12,724,065Granted
- Caching Outputs Of Components In Signal-flow-based SimulationsAug 25, 2026 · US 12,717,994Granted
- Delay Calculation With Pattern Matching For Static Timing AnalysisAug 25, 2026 · US 12,717,991Granted
- Power Routing Reduction In Circuit Design For Electrostatic Discharge CheckingAug 25, 2026 · US 12,717,998Granted
- Extended Regular Expression Matching In A Directed Acyclic Graph By Using Assertion SimulationAug 25, 2026 · US 12,717,997Granted
- Bitcell Power Tracking Scheme For Transient Voltage Collapse Write AssistAug 25, 2026 · US 12,718,877Granted
- Logic Built-in Self-test (lbist) Circuit For Authenticity ValidationAug 25, 2026 · US 12,717,890Granted
- Dynamic Ordering Of Design Rule ChecksAug 25, 2026 · US 12,717,999Granted
- Static Random Access Memory CellAug 18, 2026 · US 12,712,017Granted
- Constant Transconductance-resistance Tracking Circuit For Complementary Metal Oxide Semiconductor AmplifiersAug 18, 2026 · US 12,712,504Granted
- Memristor-enabled Programmable Sensing And Switching Threshold AdjustmentAug 11, 2026 · US 12,706,143Granted
- Layout Versus Schematic (lvs) Device Extraction Using Pattern MatchingAug 11, 2026 · US 12,705,414Granted
Related companies, and why
- NIOBIUM MICROSYSTEMS INCSimilar federal contract value in Semiconductors · $150K in contracts
- NITRIDE SOLUTIONS, INC.Similar federal contract value in Semiconductors · $149K in contracts
- GALLOX SEMICONDUCTORS INC.Similar federal contract value in Semiconductors · $140K in contracts
- TELLI TECHNOLOGIES INCSimilar federal contract value in Semiconductors · $125K in contracts
- LOGISIC DEVICES, INC.Similar federal contract value in Semiconductors · $124K in contracts
- OMEGA PHOTONICS SYSTEMS LLCSimilar federal contract value in Semiconductors · $111K in contracts
Sources
Federal grants from SBIR/STTR, NIH, NSF and DoD records. Federal contracts from USAspending.gov. Private capital from SEC Form D. Patents from USPTO. Publications from OpenAlex. Regulatory activity from the Federal Register. Press matched on company name.
How to read this page
Figures show associations in public records, not causes or predictions. Nothing here is investment advice. An em-dash means no record was found under this company's name, not that none exists.
Data freshness
SEC Form D filings through . SBIR and STTR awards through .