D2S, Inc.
Computational lithography and mask optimization software for semiconductor manufacturing
New patent ·
- Sector
- Semiconductors
- Headquarters
- SAN JOSE, CA
- Founded
- 2007
- Latest Form D
- $12.7M, Mar 2012
- Total capital
- $12.7M
- Federal grants
- None on recordNo awards found in SBIR/STTR, NIH, NSF or DoD records.
- Private capital raised
- $12.7M
- 1 Form D · last Mar 2012
- 176 months since last filing
- Federal contracts
- None on recordNo federal contract awards found.
- Granted patents
- 23
- 17 pending · first 2025
- Rank in peer group#4 of 27
Capital timeline
Latest events
- Private capital raisedForm D · SEC · 1st filing$12.7M
Node area is scaled to amount. Form D reports securities sold, which can differ from an announced round; filings are numbered in the order they were made.
Standing among 27 peers
Line = medianSemiconductors · Software
- Granted patents#4 · top 15%
Cumulative measures favor older companies. Rankings describe position today, not outcome. Below the median, ranks show as a band rather than a number.
Founders and team
From SEC Form D filings- Aki FujimuraExecutive Officer, Director, PromoterNamed in SEC Form D filings
- Alex BalkanskiDirector, PromoterNamed in SEC Form D filings
- James FongDirector, PromoterNamed in SEC Form D filings
- Lance GlasserDirector, PromoterNamed in SEC Form D filings
- Nicholas PianimExecutive Officer, Director, PromoterNamed in SEC Form D filings
What it has protected
USPTO · 23 granted of 40- New patentAuto Compaction Tool For Electronic Design AutomationUSPTOUS 12,769,908
- New patentMask Optimization For Layer Accounting For Overlap With Other LayersUSPTOUS 12,754,471
- New patentConcurrent Mask Optimization For Multiple LayersUSPTOUS 12,754,474
Show all 40 patent records
- Auto Compaction Tool For Electronic Design AutomationOct 20, 2026 · US 12,769,908Granted
- Mask Optimization For Layer Accounting For Overlap With Other LayersOct 6, 2026 · US 12,754,471Granted
- Concurrent Mask Optimization For Multiple LayersOct 6, 2026 · US 12,754,474Granted
- Mask Optimization Preferentially Accounting For Overlap RegionsOct 6, 2026 · US 12,754,473Granted
- Mask Optimization For Layer Based On Comparison Of Components In Layer To Components In Other LayersOct 6, 2026 · US 12,754,472Granted
- Using Pixel-based Definition Of An Integrated Circuit Design To Perform Machine-trained RoutingSep 17, 2026 · Application 19679083Pending
- Using A Machine-trained Network To Perform Physical DesignSep 8, 2026 · US 12,730,959Granted
- Mask Optimization For First Layer That Accounts For Other LayersAug 18, 2026 · US 12,710,694Granted
- Computing Parasitic Values For Semiconductor DesignsJul 23, 2026 · Application 19568724Pending
- Method And System For Determining A Charged Particle Beam Exposure For A Local Pattern DensityJul 21, 2026 · US 12,688,998Granted
- Geometric Loading Effect Correction For LithographyJun 25, 2026 · Application 19541045Pending
- Routing Non-preferred Direction Wiring Layers Of An Integrated Circuit By Minimizing Vias Between These LayersJun 25, 2026 · Application 19467749Pending
- Interactively Presenting For Minimum Overlap Shapes In An Ic DesignJun 23, 2026 · US 12,664,340Granted
- Concurrently Routing Multiple Partitions Of An Integrated Circuit DesignJun 23, 2026 · US 12,664,347Granted
- Mask Optimization Accounting For More Critical And Less Critical Overlap RegionsJun 16, 2026 · US 12,656,675Granted
- Generating Routes For An Integrated Circuit Design With Non-preferred Direction Curvilinear WiringJun 2, 2026 · US 12,645,858Granted
- Multi-layer Analysis Of Design Layout DecompositionsMay 21, 2026 · Application 19094706Pending
- Fitness Score For Optimization Of Design LayoutMay 21, 2026 · Application 19094702Pending
- Use Of Machine-trained Network For ColoringMay 21, 2026 · Application 19094712Pending
- Optimization Of Design Layout Decomposition Using Machine-trained NetworkMay 21, 2026 · Application 19094700Pending
- Context-sensitive Identification Of Violations In Design Layout ColoringMay 21, 2026 · Application 19094704Pending
- Using Pixel-based Definition Of An Integrated Circuit Design To Perform RoutingMay 19, 2026 · US 12,632,638Granted
- Generating Routes For An Integrated Circuit Design With Non-preferred Direction Curvilinear WiringMay 12, 2026 · US 12,626,046Granted
- Computing And Displaying A Predicted Overlap Shape In An Ic Design Based On Predicted Misalignment Of Metal LayersMay 12, 2026 · US 12,626,047Granted
- Using Machine Learning To Produce RoutesApr 28, 2026 · US 12,614,017Granted
- Computing Parasitic Values For Semiconductor DesignsApr 16, 2026 · Application 19420437Pending
- Computing Parasitic Values For Semiconductor DesignsMar 17, 2026 · US 12,579,353Granted
- Computing And Displaying A Predicted Overlap Shape In An Ic Design Based On Predicted Manufacturing ContoursMar 12, 2026 · Application 19392064Pending
- Geometric Loading Effect Correction For LithographyMar 10, 2026 · US 12,572,082Granted
- Leveraging Concurrency To Improve Interactivity With An Eda ToolFeb 10, 2026 · US 12,547,803Granted
- Computing And Displaying A Predicted Overlap Shape In An Ic Design Based On Predicted Manufacturing ContoursFeb 10, 2026 · US 12,547,804Granted
- Routing Non-preferred Direction Wiring Layers Of An Integrated Circuit By Minimizing Vias Between These LayersFeb 3, 2026 · US 12,541,634Granted
- Computing Parasitic Values For Semiconductor DesignsDec 16, 2025 · US 12,499,301Granted
- Computing Parasitic Values For Semiconductor DesignsDec 4, 2025 · Application 19296150Pending
- Methods And Systems To Determine Parasitics For Semiconductor Or Flat Panel Display FabricationDec 2, 2025 · US 12,488,175Granted
- Methods For Modeling Of A Design In Reticle Enhancement TechnologyNov 27, 2025 · Application 19287132Pending
- Computation Of Parasitic Values For Interconnect SegmentsNov 20, 2025 · Application 19033435Pending
- Parasitics Extraction For Interconnect Segments In 3D RegionsNov 20, 2025 · Application 19033438Pending
- Dynamic Computation Of Tile Size For Parasitics ExtractionNov 20, 2025 · Application 19033439Pending
- Tiling Of Layout For Parasitics ExtractionNov 20, 2025 · Application 19033434Pending
Related companies, and why
- Cohere Technologies, Inc.Similar federal contract value in Semiconductors · null in contracts
- Fugue, Inc.Similar federal contract value in Semiconductors · null in contracts
- Meter, Inc.Similar federal contract value in Semiconductors · null in contracts
- SiFive, Inc.Similar federal contract value in Semiconductors · null in contracts
- Barefoot Networks, Inc.Similar federal contract value in Semiconductors · null in contracts
- Bridgelux IncSimilar federal contract value in Semiconductors · null in contracts
Sources
Federal grants from SBIR/STTR, NIH, NSF and DoD records. Federal contracts from USAspending.gov. Private capital from SEC Form D. Patents from USPTO. Publications from OpenAlex. Regulatory activity from the Federal Register. Press matched on company name.
How to read this page
Figures show associations in public records, not causes or predictions. Nothing here is investment advice. An em-dash means no record was found under this company's name, not that none exists.
Data freshness
SEC Form D filings through . SBIR and STTR awards through .