Arteris, Inc.
Network-on-chip (NoC) interconnect intellectual property and SoC integration automation software
New patent ·
- Sector
- Semiconductors
- Headquarters
- Campbell, CA
- Latest Form D
- $5.4M, Jun 2021
- Total capital
- $11.2M
- Federal grants
- None on recordNo awards found in SBIR/STTR, NIH, NSF or DoD records.
- Private capital raised
- $11.2M
- 2 Form D · last Jun 2021
- 65 months since last filing
- Federal contracts
- None on recordNo federal contract awards found.
- Granted patents
- 15
- 25 pending · first 2025
- Rank in peer group#5 of 27
Capital timeline
Latest events
- Private capital raisedForm D · SEC · 2nd filing$5.4M
- Private capital raisedForm D · SEC · 1st filing$5.8M
Node area is scaled to amount. Form D reports securities sold, which can differ from an announced round; filings are numbered in the order they were made.
Standing among 27 peers
Line = medianSemiconductors · Software
- Granted patents#5 · top 19%
Cumulative measures favor older companies. Rankings describe position today, not outcome. Below the median, ranks show as a band rather than a number.
Founders and team
From SEC Form D filings- Amy Charles MillerExecutive OfficerNamed in SEC Form D filings
- Antonio Charles VianaDirectorNamed in SEC Form D filings
- . Charles Arteris IP, LLCPromoterNamed in SEC Form D filings
- Atiq Charles RazaDirectorNamed in SEC Form D filings
- Christian Charles ClaussenDirectorNamed in SEC Form D filings
- Craig Charles ForrestExecutive OfficerNamed in SEC Form D filings
Show all 16 people
- David Charles MertensExecutive OfficerNamed in SEC Form D filings
- Dhiraj Charles MallickDirectorNamed in SEC Form D filings
- Isabelle Charles GedayDirector, Executive OfficerNamed in SEC Form D filings
- Karel Charles JanacExecutive Officer, DirectorNamed in SEC Form D filings
- Kent Charles OrthnerExecutive OfficerNamed in SEC Form D filings
- K. Charles JanacExecutive Officer, DirectorNamed in SEC Form D filings
- Kurt Charles ShulerExecutive OfficerNamed in SEC Form D filings
- Raman Charles ChitkaraDirectorNamed in SEC Form D filings
- Stephane Charles MehatExecutive OfficerNamed in SEC Form D filings
- Wayne Charles CantwellDirectorNamed in SEC Form D filings
What it has protected
USPTO · 15 granted of 40- New patentSYSTEM AND METHOD FOR AREA AND TIMING ASSESSMENT OF A NETWORK-ON-CHIP (NoC) IMPLEMENTATIONUSPTOUS 12,769,910
- New patentSystem And Method For Deterministic And Incremental Physically-aware Network-on-chip GenerationUSPTOUS 12,764,062
- PendingFault Aggregation And Remapping In An Electronic SystemUSPTOApplication 19079497
Show all 40 patent records
- SYSTEM AND METHOD FOR AREA AND TIMING ASSESSMENT OF A NETWORK-ON-CHIP (NoC) IMPLEMENTATIONOct 20, 2026 · US 12,769,910Granted
- System And Method For Deterministic And Incremental Physically-aware Network-on-chip GenerationOct 13, 2026 · US 12,764,062Granted
- Fault Aggregation And Remapping In An Electronic SystemSep 17, 2026 · Application 19079497Pending
- Hardware Prefetching Of Extended Cache BlocksSep 3, 2026 · Application 19067986Pending
- Writing Data And Resilience Bits To Register MemorySep 1, 2026 · US 12,724,708Granted
- Modulo Operations For Interleaved Memory Having Non-power-of-two ChannelsAug 25, 2026 · US 12,717,708Granted
- Hardware Pipeline For Cache Coherent Interconnect Including Snoop FiltersAug 18, 2026 · US 12,711,070Granted
- Fast Modulo Processing For Interleaved Memory Having Non-power-of-two ChannelsAug 6, 2026 · Application 19044612Pending
- Use Of AI Image Generation Model To Create High-level Visualization Of A Network-on-chipJul 28, 2026 · US 12,694,192Granted
- System And Method For Managing Event Messages In A Cache Coherent InterconnectJun 30, 2026 · US 12,670,097Granted
- System Map Equivalence In Integrated Circuit DesignsJun 25, 2026 · Application 18986851Pending
- SYSTEM AND METHOD FOR GENERATION OF NETWORKS-ON-CHIP (NoCs)Jun 16, 2026 · US 12,657,155Granted
- Ensuring Arbitration Fairness In A Network-on-chipJun 11, 2026 · Application 19390673Pending
- Point-of-coherence Exclusive Monitor For A Cache Coherent Interconnect For A Multi-core Electronic SystemJun 2, 2026 · US 12,645,595Granted
- SYSTEM AND METHOD FOR INSERTION OF PIPELINE STAGES IN AND SYNTHESIS OF A NETWORK-ON-CHIP (NoC)May 21, 2026 · Application 19448054Pending
- Static Analysis For Buffer Insertion In A Network-on-chip TopologyMay 21, 2026 · Application 19392065Pending
- Shaping A Network-on-chip Topology Prior To Automated Topology SynthesisMay 21, 2026 · Application 19392100Pending
- Coherent Traffic Acceleration For A Directory-based Multi-core Electronic SystemMay 14, 2026 · Application 18901002Pending
- System And Method For Handling Multi-target Transactions In An Eletronic SystemMay 7, 2026 · Application 19435709Pending
- Multiple Input, Multiple Output Compiler For Preparing Files For Design Of A Hardware-software Interface In An Electronic SystemApr 16, 2026 · Application 19357070Pending
- SYNTHESIS OF A NETWORK-ON-CHIP (NoC) FOR INSERTION OF PIPELINE STAGESJan 13, 2026 · US 12,524,590Granted
- METHOD FOR CONNECTING PORTS OF A NETWORK-ON-CHIP (NoC) VIA REGULAR EXPRESSIONSJan 8, 2026 · Application 19251837Pending
- DESIGN TOOL FOR CONNECTING PORTS OF A NETWORK-ON-CHIP (NoC) VIA REGULAR EXPRESSIONSJan 8, 2026 · Application 19253732Pending
- Network On Chip Broadcasters Using Duplicated TransactionsJan 8, 2026 · Application 19323091Pending
- Design Tool For Using Sub-architectures Of A Main Architecture In Network-on-ship Design Distribution And AssemblyJan 8, 2026 · Application 19257391Pending
- Processing Writes To Multiple Targets In A Directory-based Cache Coherent Electronic SystemJan 6, 2026 · US 12,517,829Granted
- Deadlock-free Modification To Network-on-chip TopologyJan 1, 2026 · Application 19256057Pending
- Design Tool For Generation Of A Network-on-chip (noc) Including Insertion Of Adapters In A PathJan 1, 2026 · Application 19255953Pending
- Reinforced Learning For Topology Generation Of A Network-on-chipJan 1, 2026 · Application 19257390Pending
- Virtual Bridge For Design Of An Integrated CircuitJan 1, 2026 · Application 18759989Pending
- System And Method For Generation Of A Report And Debug Of Address Transformations In Electronic Systems Described With Ip-xact StandardDec 30, 2025 · US 12,511,466Granted
- DESIGN TOOL FOR GENERATION OF DEADLOCK FREE NETWORK-ON-CHIP (NoC) WITHIN A SYSTEM-ON-CHIP (SoC)Dec 4, 2025 · Application 19296900Pending
- Design Tool Using Machine Learning Models For Interactive Route Determination In A Network-on-chipOct 30, 2025 · Application 19260655Pending
- Design Tool Using Machine Learning For Incremental Placement Of Elements On FloorplanOct 30, 2025 · Application 19263553Pending
- System And Method For Scripting GeneratorsOct 21, 2025 · US 12,450,036Granted
- System And Method For Using Interface Protection ParametersOct 9, 2025 · Application 19246653Pending
- BROADCASTER WITH BUFFERING FOR NETWORK ON CHIP (NoC)Oct 9, 2025 · Application 19239925Pending
- SYSTEM AND METHOD FOR DEADLOCK DETECTION IN NETWORK-ON-CHIP (NoC) HAVING EXTERNAL DEPENDENCIESOct 7, 2025 · US 12,438,829Granted
- MODIFICATION OF EXISTING NETWORK-ON-CHIPs (NoCs) USING INCREMENTAL MODIFICATIONSSep 18, 2025 · Application 19221575Pending
- System And Method For Transaction Broadcast In A Network On ChipSep 9, 2025 · US 12,411,801Granted
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- Himet Materials LLCSimilar federal contract value in Semiconductors · null in contracts
Sources
Federal grants from SBIR/STTR, NIH, NSF and DoD records. Federal contracts from USAspending.gov. Private capital from SEC Form D. Patents from USPTO. Publications from OpenAlex. Regulatory activity from the Federal Register. Press matched on company name.
How to read this page
Figures show associations in public records, not causes or predictions. Nothing here is investment advice. An em-dash means no record was found under this company's name, not that none exists.
Data freshness
SEC Form D filings through . SBIR and STTR awards through .