ARIES DESIGN AUTOMATION, LLC

Latest events

• Jul 2022Federal grantNASA · Phase I · Design and Formal Verification of a Fault-Tolerant RISC-V Processor Core Augmented to Accelerate Image and Science Data Processing$150K
• Sep 2021Federal grantDefense · Phase II · Design and Formal Verification of a RISC-V DSP for Space Communication$1M
• May 2013Federal contractNASA · Igf::ot::igf In The Proposed Project, We Will Formally Verify The Correctness Of The Interaction Between A Real-time Operating System (rtos) And User Processes Under Various Operating Scenarios, Such As Multitasking, Interrupt Handling, User And Kernel Mode Switching. The Formal Verification Will Be Done Assuming Execution On The Powerpc 750 Architecture That Is Implemented In The Radiation-hardened RAD750 Flight-control Computers Utilized In Many NASA Space Missions, And Are Planned To Be Used$125K
• May 2013Federal contractNASA · Igf::ot::igf We Will Develop An Efficient Graphics Processing Unit (gpu) Based Parallel Binary Decision Diagram (bdd) Software Package, And Will Also Combine It With Our Gpu-based Parallel Sat Solver That We Are Currently Developing In A NASA SBIR Phase II Project In Order To Solve Much Larger And More Complex Boolean Formulas From Formal Verification Than Possible With Either Method Alone. Bdds Are A Data Structure That Satisfies Some Simple Restrictions, Resulting In A Unique Representation O$125K
• Feb 2012Federal contractNASA · We Will Develop A Prototype Of A Gpu-based Parallel Binary Decision Diagram (bdd) Software Package. Bdds Are A Data Structure That Satisfies Some Simple Restrictions, Resulting In A Unique Representation Of A Boolean Function Regardless Of Its Actual Implementation. This Property Of Bdds Allows The Efficient Solution Of Many Problems. The Proposed Tool Will Exploit Multi-core Cpus And The Thousands Of Stream Cores In The Latest Graphics Processors (gpus) , Which Were Made Accessible To Programme$125K
• Aug 2011Federal contractCommerce · SBIR FY11$90K
• Jun 2011Federal contractNASA · We Will Implement An Environment For Design, Formal Verification, Compilation Of Code, And Performance And Power Evaluation Of Systems On A Chip (socs) Consisting Of Heterogeneous Processor Cores That Can Be Single-issue Pipelined, Superscalar, Or Vliw, And Are Binary-code Compatible With Any Existing Instruction Set Architecture (isa). Particularly, We Will Ensure Binary-code Compatibility With The Powerpc 750 Isa, Which Is Used In The Radiation-hardened RAD750 Flight-control Computer That Is U$600K

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